Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charged-coupled devices (CCDs), solar cells, and digital micro-mirror devices (DMDs).
Semiconductor devices perform a wide range of functions such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual projections for television displays. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.
Semiconductor devices exploit the electrical properties of semiconductor materials. The atomic structure of semiconductor material allows its electrical conductivity to be manipulated by the application of an electric field or base current or through the process of doping. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.
A semiconductor device contains active and passive electrical structures. Active structures, including bipolar and field effect transistors, control the flow of electrical current. By varying levels of doping and application of an electric field or base current, the transistor either promotes or restricts the flow of electrical current. Passive structures, including resistors, capacitors, and inductors, create a relationship between voltage and current necessary to perform a variety of electrical functions. The passive and active structures are electrically connected to form circuits, which enable the semiconductor device to perform high-speed calculations and other useful functions.
Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual die from the finished wafer and packaging the die to provide structural support and environmental isolation.
One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller die size can be achieved by improvements in the front-end process resulting in die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.
In a flipchip packages, a semiconductor die is typically mounted to a package substrate with the active side of the die facing the substrate. The interconnection of the circuitry in the semiconductor die with circuitry in the substrate is made by way of bumps which are attached to an array of interconnect pads on the die, and bonded to a corresponding complementary array of interconnect pads on the substrate.
The pads on the semiconductor die for the signal, power, and ground functions are conventionally distributed throughout the array, and the corresponding pads on the substrate are connected to appropriate circuitry to the external second level interconnects. The second level interconnects have a greater pitch than the flipchip interconnects, and so the routing on the substrate conventionally fans out. The fan-out routing between the pads on the semiconductor die and the external pins of the package is formed on multiple metal layers within the package substrate.
Multiple layer substrates are expensive and, in conventional flipchip constructs, the substrate alone typically accounts for more than half the package cost. The high cost of multilayer substrates has been a factor in limiting proliferation of flipchip technology in mainstream products. In conventional flipchip constructs, the escape routing pattern typically introduces additional electrical parasitics because the routing includes short runs of unshielded wiring and vias between wiring layers in the signal transmission path. Electrical parasitics can significantly limit package performance.
In a conventional flipchip package, the input/output pads, collectively the signal pads, on semiconductor die 13 are arranged in an area array substantially covering active surface 12 of the die, as shown in a plan view generally at 10 in FIG. 1. Signal pads 18 and 19, power pads 14, and ground pads 16, directed respectively to the signal, power and ground functions of semiconductor die 13, are distributed throughout the multiple rows and columns within the array. In particular, some of signal pads 18 are arranged on the perimeter of the array, while other signal pads 19 are not. Ordinarily, some design effort is made to arrange the pads so that the various signal pads are surrounded by, or at least adjacent to, power pads and/or ground pads.
Many conventional flipchip packages are made using ceramic substrates. Ceramic substrates can be made with a large number of layers relatively inexpensively, and blind vias can be made in ceramic layers without difficulty. In a conventional chip made for use with a conventional ceramic substrate, the pad pitch is typically in the range 150 micrometers (μm) to 250 μm, and a 225 μm grid pitch is typical of many chips.
The fan-out routing in the substrate, that is, the wiring on the substrate that connects the corresponding pads on the substrate with the external terminals of the package, is implemented in multiple metal layers patterned to provide the signal wiring and power and ground wiring. An arrangement of substrate pads corresponding to die pad layout 10 is shown in a plan view generally at 20 in FIG. 2. Signal pads 28 and 29, power pads 24, and ground pads 26 are arranged in a complementary array on substrate surface 22 so that they can receive and be bonded respectively to the signal, power, and ground bumps attached to the corresponding pads on the die. In the conventional arrangement, some of the pads 28 associated with signal routing are located at the perimeter of the array, while other pads 29 are not. The escape routing for the signal pads on the perimeter of the array can directly cross beneath die edge 23 as traces 30 in the uppermost metal layer of the substrate. Pads on the substrate that are not at the perimeter of the array are connected to deeper metal layers in the substrate by way of short traces and vias. Signal pads 29 are connected by way of short traces (signal stubs or jogs) 32 through signal vias 34 to signal traces in one of several metal layers beneath. Likewise, power pads 24 are connected by way of short traces (power stubs or jogs) 36 through power vias 38 to power traces in a metal layer beneath, and ground pads 26 are connected by way of short traces (ground stubs or jogs) 40 through ground vias 42 to power traces in a metal layer beneath.
In a typical conventional package having approximately 1000 external terminals, there are at least 2 or 3 layers of signal wiring and at least 4 or 5 layers of power and ground wiring in the substrate, which leads to a total number of layers of approximately 6 or 8 or more. As a general rule, an increase in number of signal wiring layers requires a concomitant increase in power and ground layers owing to the need to maintain a transmission line electrical environment in the package, which further increases the total layer count. The need for additional layers also results in longer signal paths, and many layer-to-layer vias, adding undesirable electrical parasitics and deterioration of performance.